1. Field of the Invention
The present invention relates to an image reading device, and more particularly to an image reading device provided with means for accumulating incident light information, adapted for use in a reader unit of an image information processing apparatus such as facsimile.
2. Related Background Art
There are already known various image reading methods for use in the image reading devices. Examples of such methods are frame transfer method and interline transfer method employed in CCD (charge coupled devices).
Also image reading circuit structures for use in the amplifying devices with improved S/N ratio are disclosed for example in the U.S. Pat. Nos. 4,791,469, 4,831,454, 4,835,404 and 4,876,601.
Furthermore, circuit structures adapted for use in thin film devices suitable for forming large area devices are disclosed, for example, in the U.S. Pat. Nos. 4,390,791, 4,461,956, 4,829,485 and 4,886,977.
Furthermore, the U.S. Pat. No. 4,963,955 discloses a circuit structure in which transistors constituting pixels are serially connected for every vertical line for enabling collective resetting. However these structures have a limit in reducing the resetting time, because of large parasite resistance and capacitance in the serially connected line of pixels.
In addition to the conventional structures mentioned above, there is also proposed a resetting method utilizing block drive.
FIG. 8 is a circuit diagram of a conventional image reading device, showing, as an example, a photosensor array with nine photosensors.
In the circuit shown in FIG. 8, among photosensors E1-E9, three constitute a block, and three blocks constitute the photosensor array. Capacitors C1-C9 and switching transistors T1-T9, respectively corresponding to the photosensors E1-E9, are similarly grouped.
Electrodes at a side (common electrodes) of the photosensors E1-E9 are connected to a power source 101, while the other electrodes (individual electrodes) are grounded through respectively capacitors C1-C9.
Also, the individual electrodes of a same cardinal number in different blocks of the photosensors E1-E9 are connected, through respective switching transistors T1-T9, to one of common lines 102-104.
More detailedly, first switching transistors T1, T4, T7 of different blocks are connected to the common line 102; second switching transistors T2, T5, T8 of different blocks are connected to the common line 103; and third switching transistors T3, T6, T9 of respective blocks are connected to the third common line 104.
Said common lines 102-104 are connected, respectively through switching transistors T10-T12, to an amplifier 105.
The gate electrodes of the switching transistors T1-T9 are commonly connected for each block, and are respectively connected to parallel output terminals of a shift register 106. Said output terminals release high-level signals in succession at predetermining timings, whereby the switching transistors T1-T9 are turned on in succession in the unit of each block.
Also, the gate electrodes of the switching transistors T10-T12 are respectively connected to parallel output terminals of a shift register 107. Said output terminals release high-level signals in succession at predetermined timings, whereby the switching transistors T10-T12 are turned on in succession.
The common lines 102-104 are also grounded respectively through capacitors C10-C12 and switching transistors CT1-CT3.
The capacitance of the capacitors C10-C12 is selected to be sufficiently larger than that of the capacitors C1-C9.
The gate electrodes of the switching transistors CT1-CT3 are commonly connected to a terminal 108. Thus, the application of a high-level signal to said terminal 108 turns on the switching transistors CT1-CT3 simultaneously, thereby grounding the common lines 102-104.
Such image reading device is disclosed in the U.S. Pat. No. 4,827,345.
In the following there will be explained the function of such conventional image reading device, with reference to a timing chart of the switching transistors T1-T12 and CT1-CT3, shown in FIG. 9. In FIG. 9 there is shown the timing when each switching transistor is turned on, and it also shows the timing of the release of a high-level signal from the shift register 106 or 107.
When the light enters the photosensors E1-E9, charges are accumulated in the capacitors C1-C9 from the power source 101 through the photosensors E1-E9, according to the intensity of said incident light.
Then the switching transistors T1-T3 are turned on when a high-level signal is released from the first output terminal of the shift register 106 (FIG. 9(a)).
With said switching transistors T1-T3 being turned on, the charges accumulated in the capacitors C1-C3 are respectively transferred to the capacitors C10-C12.
Subsequently the shift register 107 effects a shifting operation to turn on the switching transistors T10-T12 in succession [FIG. 9(d)-(f)], whereby the optical information of the first block transferred to and accumulated in the capacitors C10-C12 are read in succession and released through the amplifier 105.
After the reading of the information of the first block, an unrepresented circuit detects said reading and applies a high-level signal to the terminal 108, whereby the switching transistors CT1-CT3 are simultaneously turned on [FIG. 9(g)]. Thus the remaining charges in the capacitors C1-C3 and C10-C12 are dissipated, and said capacitors become ready for accumulating the optical information.
Then the shift register 106 effects a shift to release a high-level signal from the second output terminal, thereby turning on the switching transistors T4-T6 [FIG. 9(b)]. Thus the information reading of the second block is conducted in a similar manner as in the first block. Operations for the third block are also conducted in a similar manner.
As explained above, information are accumulated in the capacitors C1-C9, according to the shift timing of the shift registers 106, 107 and the timing of the high-level signal application to the terminal 108 as shown in FIG. 9. The information accumulated in said capacitors C1-C9 are transferred to the capacitors C10-C12 by the unit of each block at a time, and the information thus transferred are time-sequentially read by the switching transistors T10-T12.
However, the conventional structure has been associated with the following drawbacks, because of the on-resistance (resistance in "on" state) in the switching transistors:
(1) The timing constants, determined by the capacitances of the capacitors C1-C9 and the resistances of the corresponding switching transistors T1-T9 become large, and the discharging time of the capacitors C1-C9 becomes longer because of the parasite capacitances of the common lines 102-104 and the switching transistors T10-T13, the capacitances of the capacitors C10-C12 and the wiring resistances. Consequently, such image reading device requires a long time for the information reading operation;
(2) As the discharge of the capacitors C1-C9 requires a long time, it is limited to a certain time in practice, but the image reading operation becomes unreliable because the amount of the remaining charge in the capacitors C1-C9 varies depending on the light intensity.